Just found this: the way I interpret it, I can assign ADC to any pin 4-14 (and a few others).
PSRAM - Stands for pseudo-static RAM and refers to the SPI RAM.
ADC: Pins that can be used as ADC channels.
RTC: Pins that are RTC GPIOs and can be used in deep-sleep mode.
PU/PD: Pins that have software configurable pull-up/pull-down functionality.
If EFUSE_STRAP_JTAG_SEL is set, GPIO3 is used to select the interface that is used as JTAG interface.
NoteIf EFUSE_DIS_USB_JTAG or EFUSE_DIS_PAD_JTAG are set, the interface selection is fixed and GPIO3 is not used as bootstrapping pin.
GPIO45 is used to select the voltage VDD_SPI for the Flash/PSRAM interfaces SPI0 and SPI1.
GPIO pins
ESP32-S3 has 45 GPIO pins, where a subset can be used as ADC channel and as low-power digital input/output in deep-sleep mode, the so-called RTC GPIOs. Some of them are used by special SoC components and are not broken out on all ESP32-S3 modules. The following table gives a short overview.Pin | Type | ADC | RTC | PU / PD | Special function | Remarks |
---|---|---|---|---|---|---|
GPIO0 | In/Out | - | X | X | - | Bootstrapping |
GPIO1 | In/Out | X | X | X | - | - |
GPIO2 | In/Out | X | X | X | - | - |
GPIO3 | In/Out | X | X | X | - | Bootstrapping |
GPIO4 | In/Out | X | X | X | - | - |
GPIO5 | In/Out | X | X | X | - | - |
GPIO6 | In/Out | X | X | X | - | - |
GPIO7 | In/Out | X | X | X | - | - |
GPIO8 | In/Out | X | X | X | - | - |
GPIO9 | In/Out | X | X | X | - | - |
GPIO10 | In/Out | X | X | X | - | - |
GPIO11 | In/Out | X | X | X | - | - |
GPIO12 | In/Out | X | X | X | - | - |
GPIO13 | In/Out | X | X | X | - | - |
GPIO14 | In/Out | X | X | X | - | - |
GPIO15 | In/Out | X | X | X | XTAL_32K_P | External 32k crystal |
GPIO16 | In/Out | X | X | X | XTAL_32K_N | External 32k crystal |
GPIO17 | In/Out | X | X | X | - | - |
GPIO18 | In/Out | X | X | X | - | - |
GPIO19 | In/Out | X | X | X | USB D- | USB 2.0 OTG / USB-JTAG bridge |
GPIO20 | In/Out | X | X | X | USB D+ | USB 2.0 OTG / USB-JTAG bridge |
GPIO21 | In/Out | - | X | X | - | - |
GPIO26 | In/Out | - | - | X | Flash/PSRAM SPICS1 | not available if SPI RAM is used |
GPIO27 | In/Out | - | - | X | Flash/PSRAM SPIHD | not available |
GPIO28 | In/Out | - | - | X | Flash/PSRAM SPIWP | not available |
GPIO29 | In/Out | - | - | X | Flash/PSRAM SPICS0 | not available |
GPIO30 | In/Out | - | - | X | Flash/PSRAM SPICLK | not available |
GPIO31 | In/Out | - | - | X | Flash/PSRAM SPIQ | not available |
GPIO32 | In/Out | - | - | X | Flash/PSRAM SPID | not available |
GPIO33 | In/Out | - | - | X | Flash/PSRAM SPIQ4 | not available if octal Flash or SPI RAM is used |
GPIO34 | In/Out | - | - | X | Flash/PSRAM SPIQ5 | not available if octal Flash or SPI RAM is used |
GPIO35 | In/Out | - | - | X | Flash/PSRAM SPIQ6 | not available if octal Flash or SPI RAM is used |
GPIO36 | In/Out | - | - | X | Flash/PSRAM SPIQ7 | not available if octal Flash or SPI RAM is used |
GPIO37 | In/Out | - | - | X | Flash/PSRAM SPIQ8 | not available if octal Flash or SPI RAM is used |
GPIO38 | In/Out | - | - | X | Flash/PSRAM SPIDQS | not available if octal Flash or SPI RAM is used |
GPIO39 | In/Out | - | - | X | MTCK | JTAG interface |
GPIO40 | In/Out | - | - | X | MTDO | JTAG interface |
GPIO41 | In/Out | - | - | X | MTDI | JTAG interface |
GPIO42 | In/Out | - | - | X | MTMS | JTAG interface |
GPIO43 | In/Out | - | - | X | UART0 TX | Console |
GPIO44 | In/Out | - | - | X | UART0 RX | Console |
GPIO45 | In/Out | - | - | X | - | Bootstrapping (0 - 3.3V, 1 - 1.8V) |
GPIO46 | In/Out | - | - | X | - | Bootstrapping |
GPIO47 | In/Out | - | - | X | SPICLK_P | - |
GPIO48 | In/Out | - | - | X | SPICLK_N | - |
ADC: Pins that can be used as ADC channels.
RTC: Pins that are RTC GPIOs and can be used in deep-sleep mode.
PU/PD: Pins that have software configurable pull-up/pull-down functionality.
Strapping pins
GPIO0, GPIO3, GPIO45 and GPIO46 are bootstrapping. GPIO0 and GPIO46 pins are used to boot ESP32-S3 in different modes:GPIO0 | GPIO46 | Mode |
---|---|---|
1 | X | SPI Boot mode to boot the firmware from flash (default mode) |
0 | 1 | Download Boot mode for flashing the firmware |
If EFUSE_STRAP_JTAG_SEL is set, GPIO3 is used to select the interface that is used as JTAG interface.
GPIO3 | Mode |
---|---|
1 | USB-JTAG bridge at GPIO19 and GPIO20 is used as JTAG interface |
0 | GPIO39 to GPIO42 are used as JTAG interface |
NoteIf EFUSE_DIS_USB_JTAG or EFUSE_DIS_PAD_JTAG are set, the interface selection is fixed and GPIO3 is not used as bootstrapping pin.
GPIO45 is used to select the voltage VDD_SPI for the Flash/PSRAM interfaces SPI0 and SPI1.
ADC Channels
ESP32-S3 integrates two 12-bit ADCs (ADC1 and ADC2) with 20 channels in total:- ADC1 supports 10 channels: GPIO1 ... GPIO10
- ADC2 supports 10 channels: GPIO11 ... GPIO20